Towards GREEN Electronics: Design, Modeling and Fabrication of Steep Subthreshold Slope Switches

Aggressive technology scaling as per Moore’s law has resulted in elevated power dissipation levels especially due to a substantial increase in the subthreshold leakage power. Hence, designing low-power and energy-efficient integrated circuits (or Green Electronics) constitutes a key area for sustaining the irreversible growth of the global electronics and IT industry. Although improving the subthreshold performance by lowering subthreshold leakage of CMOS devices has been extensively researched, a significant improvement seems unlikely owing to the “non-abrupt” nature of the switching characteristics of MOSFETs, thereby making the devices very energy inefficient. The metric that is used to capture the abruptness of this switching behavior is known as the subthreshold swing (inverse of the subthreshold slope = dlogId/ dVgs), which has a fundamental lower limit of 2.3kT/q = 60 mV/decade for MOSFETs, indicating that in order to reduce the source-to-drain current by one decade, one must reduce the gate voltage by 60 mV. This value is essentially due to the “thermionic emission” of carriers from the source to the channel region in MOSFETs. Research efforts in the Nanoelectronics Research Lab (NRL) led by Prof. Banerjee aims to address this issue at the most fundamental level by designing Steep Subthreshold Slope or Small Subthreshold Swing switches, which can lead to power reduction by more than a million times. Various research groups around the world have attempted to develop novel switches in which the conduction mechanisms are not based on drift/diffusion to beat the fundamental limit of 60 mV/decade in CMOS transistors. The devices of interest to our group are Tunnel FET (TFET) [1]-[4], Impact-ionization based MOS (I-MOS) [5], and Nano-Electro-Mechanical Switches (NEMS) [6]-[8], which exhibit subthreshold swing lower than 60 mV/decade. To compare these devices, their band diagrams in the ON and OFF states along with that of conventional CMOS are illustrated in Fig. 1. The research in our group in this arena is holistic in nature and consists of modeling the underlying transport physics and devices; optimization of the devices for high-performance and low-power applications; fabrication, characterization and model calibration; as well as circuit/system design exploration specifically enabled by such switches. The schematic overview of the research activities is shown in Fig. 2. For modeling the T-FETs, comprehensive and in-depth understanding of the tunneling physics is of absolute necessity, which is presently lacking. The ongoing research in our group consists of developing physics based models [1] for tunneling phenomenon by adequately accounting for all the relevant factors such as the band structure effects, electron-phonon interactions as well as non-local effects. A major challenge in designing T-FETs is to increase their ON-current (ION), which when addressed would open up the pathways for ultra energy-efficient as well as high-performance integrated electronics. Design of T-FETs based on low bandgap materials (SiGe, IIIV, Graphene) are being studied in our group to improve the ION and subthreshold swing. For instance, we have recently proposed a Si/SiGe heterostructure T-FET [2] as well as a graphene based heterostructure T-FET [3], which can overcome the traditional low drive-current problem in T-FETs. Most recently, in collaboration with industrial partners in Singapore, we have demonstrated a CMOS-technology compatible, Si-nanowire based T-FET exhibiting the lowest reported value of subthreshold swing in the literature till date [4]. NEMS devices also offer unique characteristics both in device and circuit design. We have shown the superior performance of dynamic-OR gates, sleep-switches, and SRAM cells based on hybrid NEMS-CMOS designs [6]. Recent contributions from our group (in collaboration with Sematech) also include the demonstration of a novel laterally-actuated double-gate NEMS device and its circuit level exploitation to build an XOR gate with only 2 NEMS (which otherwise takes 6-10 transistors in CMOS) [7]. We have further demonstrated that the Fig. 1. Conduction mechanisms for different switches: (a) CMOS device uses drift/diffusion mechanism, (b) Tunneling transistors employ band-to-band tunneling mechanism, (c) Impact ionization based devices use avalanche breakdown mechanism, and (d) NEMS devices involve drift mechanism in ON state and there is no conduction in the OFF state except Brownian motion. Fig. 2. Schematic overview of the research in NRL on ultra energy-efficient steep subthreshold slope switches. availability of such compact XOR/XNOR gates has profound implications for simplifying Boolean functions using Karnaugh maps and can lead to a new paradigm in the design of energy-efficient digital circuits [8]. References: [1] D. Sarkar, M. Krall and K. Banerjee, Appl. Phys. Lett., 97, 263109, 2010. [2] Y. Khatami and K. Banerjee, IEEE Trans. Electron Devices Vol. 56, pp. 2752-2761, 2009. [3] Y. Khatami, M. Krall, H. Li, C. Xu and K. Banerjee, 68 Device Research Conference, pp. 66, 2010. [4] R. Gandhi, Z. Chen, N. Singh, K. Banerjee and S. Lee, IEEE Elec. Dev. Lett., Vol. 32, 2011 (in press). [5] D. Sarkar, N. Singh and K. Banerjee, IEEE Elec. Dev. Lett., Vol. 31, No. 11, pp. 1175-1177, 2010. [6] H. F. Dadgour and K. Banerjee, IET Comput. Digit. Tech. Vol. 3, No. 6, pp. 593–608, 2009. [7] H. F. Dadgour, M. M. Hussain, C. Smith and K. Banerjee, DAC, pp. 893-896, 2010. [8] H. F. Dadgour, M. M. Hussain and K. Banerjee, ISLPED, pp. 7-12, 2010.